1. Technical Field
The present invention relates to a semiconductor apparatus, and more particularly, to a semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same.
2. Related Art
In general, synchronous memory apparatuses operating in synchronization with an external system clock have been used to improve the operation speed of a semiconductor system. The synchronous memory apparatuses have evolved from single data rate (SDR) memory apparatuses into double data rate (DDR) memory apparatuses. The SDR memory apparatuses are configured to input/output data over one cycle of a clock in synchronization with a rising edge of the clock. The DDR memory apparatuses are configured to input/output data in synchronization with a rising edge and a falling edge of a clock.
It is important to accurately synchronize a controller and a memory apparatus in a data input operation of a memory system using a DDR memory apparatus. To this end, data are transmitted from the controller to the memory apparatus in synchronization with a data input strobe signal. In a data output operation, the memory apparatus generates a data output strobe signal in response to a data output command, that is, a read (RD) command received from the controller. The memory apparatus transmits data to the controller in synchronization with the data output strobe signal.
FIG. 1 is a diagram illustrating a protocol in a general semiconductor system.
Referring to FIG. 1, a general semiconductor system 10 includes a controller 12 and at least one memory apparatus 14.
The controller 12 provides a clock signal CLK, a command CMD, and an address signal ADD to the memory apparatus 14. Also, the controller 12 provides data DATA to the memory apparatus 14 in synchronization with a data input/output strobe signal DQS in response to a data input command. The memory device 14 provides data DATA to the controller 12 in synchronization with the data input/output strobe signal DQS in response to a data output command received from the memory device 14.
FIGS. 2 and 3 are timing diagrams illustrating a data input/output operation in the semiconductor system 10 illustrated in FIG. 1.
FIG. 2 is a timing diagram illustrating a data input operation in the semiconductor system 10 illustrated in FIG. 1.
Referring to FIG. 2, the data input/output strobe signal DQS has the same phase as the clock signal CLK. The controller 12 provides data DATA to the memory apparatus 14 in synchronization with the data input/output strobe signal DQS. Specifically, the controller 12 transmits data to the memory apparatus 14 by synchronizing a center of the data with an edge of the data input/output strobe signal DQS.
That is, when storing data in the memory apparatus 14, the controller 12 transmits the data to the memory apparatus 14 not by synchronizing a falling edge or a rising edge of the data with a falling edge or a rising edge of the data input/output strobe signal DQS, but by synchronizing a center of the data with a falling edge or a rising edge of the data input/output strobe signal DQS. Thus, there is a sufficient margin for synchronizing the data input/output strobe signal DQS and the input data in the memory apparatus 14.
FIG. 3 is a timing diagram illustrating a data output operation in the semiconductor system 10 illustrated in FIG. 1.
Referring to FIG. 3, the memory apparatus 14 generates the data input/output strobe signal DQS by using the clock signal CLK in response to the data output command received from the controller 12. Then, the memory apparatus 14 outputs the data input/output strobe signal DQS after a predetermined delay time. Also, the memory apparatus 14 outputs data DATA to the controller 12 by synchronizing a rising edge and a falling edge of the data with a rising edge and a falling edge of the delayed data input/output strobe signal DQS. At this point, the delayed data input/output strobe signal DQS is also transmitted to the controller 12.
The controller 12 uses an internal delay circuit to shift the phase of the data input/output strobe signal DQS, received from the memory apparatus 14, by 90° so that an edge of the data outputted from the memory apparatus 14 is synchronized with the center of the data input/output strobe signal DQS. That is, the phase of the data input/output strobe signal DQS received from the memory apparatus 14 is controlled to improve the data output margin.
If the memory apparatus 14 includes a clock synchronization circuit such as a phase-locked loop (PLL) circuit or a delay-locked loop (DLL) circuit, the memory apparatus 14 may transmit data to the controller 12 by synchronizing an edge of the data with the center of the data input/output strobe signal DQS. However, a PLL circuit or a DLL circuit consumes a large amount of power and is not suitable for application to low-power devices such as mobile devices.
Therefore, the controller 12 must control the phase of the data input/output strobe signal DQS in a data output operation. However, in this case, the controller 12 must latch the data received from the memory apparatus 14, shift the phase of the data input/output strobe signal DQS, and then output the data by synchronizing an edge of the data with the center of the data input/output strobe signal DQS. Therefore, the controller 12 must have a PLL circuit, thus increasing the total power consumption of the memory system 10.
In addition, the operation speed of the memory system 10 decreases and the operation load of the controller 12 increases. These problems become more severe as the data processing rate increases.
Furthermore, when the controller 12 changes from a power-down mode to an active mode for a data output operation, it increases a clock signal activation time for driving the PLL circuit to control the phase of the data input/output strobe signal DQS and a clock signal deactivation time for returning to the power-down mode after completion of the data output operation. This obstructs an increase in the bandwidth of the memory system 10, and impedes an increase in the operation speed of the memory system 10.